TFET MEMORY IN REDUCED POWER MODE
In this thesis, an integrated model with TFET devices and CMOS devices is pro- posed. The goal is to minimize static power as well as dynamic power in comparison to a CMOS only system. The analysis of the integrated model is conducted using Cadence Virtuoso Schematic L-Editing, Analog Design Environment and Spectre Circuit Simulator tools using the 20nm GaN TFET model and the 45nm CMOS free PDK device obtained from North Carolina State University. The experiment is confined to the schematic stage as the GaN TFET devices do not have layout cells or design rules which are required for fabrication, and post post-Silicon validation.
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