This paper presents a inductor-less broadband low-noise amplifier (LNA) implemented in 0.13 μm CMOS technology. The LNA use a CG input stage for wideband impedance matching, followed by two common source parallel amplifiers which perform distortion and noise cancellation. The LNA maintains minimum internal gain, noise figure at a given suply.

While the LNA itself likewise adds some noise to the got signal, it is essential that this LNA infused noise is as least as conceivable to congratulate appropriate recovery of the signal in the later phases of the framework. Commonly because of the confinements in the execution of ADC it works at a lower frequency extend practically identical to the input RF go, in this manner one needs a blender to down proselyte the got RF signal.



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Ruofan Dai presented a paper on “A 0.5-V novel complementary current-reused CMOS LNA for 2.4 GHz medical application” in Microelectronics Journal 55 (2016) 64–69.

Yamin Ku presented a paper on “Analysis and design of Inductorless Wideband Low – Noise Amplifier with Noise Cancellation Technique ” in DOI 10.1109/ ACCESS.2017 .2692765 , IEEE .

Zhichao Zhang presented a paper on “Wide range linearity improvement technique for linear wideband LNA” in IEICE Electronics Express, Vol.14, No.4, 1–10.

Yunlong Zheng presented a paper on “A duplex current-reused CMOS LNA with complementary derivative superposition technique: C-R LNA” in DOI: 10.1002/cta.2235 , International Journal of Circuit Theory and Applications • June 2016.

Suraj Sharma presented a paper on “Design of Low Noise Amplifier at 3-10GHz for Ultra Wideband Receiver” in September 2013 in IJIRCCE journal .

Mostafa yargholi presented a paper on “Resistive Feedback LNA With Dual Band Notch Filter for Suppressing WLAN Signals in UWB Receivers” in 2012 IEEE.

Rozi Rifin presented a paper on “Design of an Inductor-Less LNA Using Resistive Feedback Topology for UWB Applications” in 2013 in RJASET Journal.

R.S.Sai Ram presented a paper on “ Analysis and Design of CMOS Cascode LNA for UWB Applications with Gain Enhancement and Out- Band Rejection Capability.” In July12 in IJERT.

Anuj Madan presented a paper on “A 5 GHz 0.95 dB NF Highly Linear Cascode Floating-Body LNA in 180 nm SOI CMOS Technology” in IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 22, NO. 4, APRIL 201.

Ravinder Kumar et. Al. presented a paper on “DESIGN AND NOISE OPTIMIZATION OFRF LOW NOISE AMPLIFIER FOR IEEE STANDARD 802.11A WLAN” journal VLSICS Vol.3, No.2, April 2012.

Somit pandey presented a paper on “Analysis of Working of LNA in UWB Range” in AIJRFANS journal (13-212) in 2013.

Sohiful Anuar Zainol Murad presented a paper on “A Review of Low Noise Amplifiers' Topologies for Wireless Sensor Network” published in 2014 2nd International Conference on Electronic Design in journal Research Gate (375-379).

K. Yousef presented a paper on “A 2-16 GHz CMOS Current Reuse Cascaded Ultrawideband Low Noise Amplifier” year 2011 IEEE journal.

Xuan Chen, Quanyuan Feng and Shiyu Li, “Design of a 2.5GHz Differential CMOS LNA,” Progress In Electromagnetics Research Symposium, Cambridge, USA, pp. 203-206, Jul. 2008.

L.R. Carley, G. Gielen, R.A. Rutenbar, and W. Sansen. “ Synthesis tools for mixed-signal

ICs: Progresson frontend and backend strategies ”. In Design Automation Conference, DAC, pages 298–303, 1996.

A. Nunez-Aldana, N. Dhanwada, A. Doboli, S. Ganesan, and R. Vemuri. “ A Methodology For Behavioral Synthesis Of Analog Systems ”. In Southwest Symposium on Mixed-Signal Design, pages162–167, 1999.

E.S. Ochotta, R.A. Rutenbar, and L.R. Carley. “Synthesis of high-performance analog circuits inASTRX/OBLX”. In IEEE Transactions on Computer Aided Design of

Integrated Circuits and Systems,pages 273–294, 1996.

G. Van der Plas “AMGIE-A synthesis environment for CMOS analog integrated circuits”. InIEEE Transactions on Computer Aided Design of Integrated Circuits and

Systems, pages 1037–1058,2001.

R. Phelps, M. Krasnicki, R.A. Rutenbar, L.R. Carley, and J.R. Hellums. “ANACONDA: robust syn-thesis of analog circuits via stochastic pattern search”. In Proceedings of the IEEE Custom IntegratedCircuits, pages 567–570, 1999.

R. A. Rutenbar and Georges G. E. Gielen and B. A. Antao. Computer-Aided Design of Analog Inte-grated Circuits and Systems. John Wiley & Sons, 2002.

Derek K. Shaeffer, “1.5-V, 1.5-GHz CMOS Low Noise Amplifier,”IEEE Journal of solid-state circuits, Vol. 32, No. 5, May 1997.

Somesh kumar and Dr. Ravi Kumar, “A 1.8V and 2GHz Inductively Degenerated CMOS Low Noise Amplifier,” International Journal of Electronics Communication and Computer Engineering, Vol. 2, Issue 4, pp. 150-154, july 2012.

Jung-Suk Goo, Hee-Tae Ahn, Donald J. Ladwing, Zhiping Yu, Thomas H. Lee and Robert W. Dutton, “A noise optimization technique for integrated low noise amplifiers,”IEEE J. Solid-State Circuits, vol. 37, no.8, pp. 994-1002, Aug. 2002.

Reza Molavi, Shahriar Mirabbasi and Majid Hashemi, “ A Wideband CMOS LNA Design Approach,” IEEE International Symposium on Circuits and Systems, vol. 5, pp. 5107 – 5110, May 2005.

Hong Qi and Zhang Jie, “A 1.5V Low Power CMOS LNA Design,” International Symposium on Microwave, Antenna, Propagation and EMC Technologies for Wireless Communications, pp. 1379 - 1382 , Aug. 2007.

M. Muhamad and N.A Nordin, “An Area Efficient of 0.18µm LNA Using Power Constraint Method,” IEEE Mathematical/Analytical Modeling and Computer Simulation (AMS), PP. 606 – 609, May 2010

Xiaohua Fan, Heng Zhang, and Edgar Sanchez-Sinencio, “A Noise Reduction and Linearity Improvement Technique for a Differential Cascode LNA”, IEEE J. Solid-State Circuits, vol.43, pp. 588-599, March 2008.

Pietro Andreani, and Henrik Sjoland, “ Noise optimization of an inductively degenerated CMOS low noise amplifier,” IEEE Trans Circuits Syst. II, Analog Digit. Signal Process, vol. 48, pp. 835–841, 2001.

Chen Xuan, “A New ConFigureuration of Differential CMOS LNA,” 6th IEEE International Conference on Industrial Informatics, pp.635 – 638, July 2008.

Anderson, R. W., "S-parameter techniques for faster, more accurate network design," Hewlett-Packard Application Note 95-1, 5952-1130, 1997.

Anon., "S Parameter Design," Agilent Technologies application note, AN 154, 2006.

Xuechu LI, Qingyun Gao and Shicai Qin, “An Improved CMOS RF Low Noise Amplifier,” Proc. Intl. Conf. ASIC, vol. 2, pp. 1102 - 1105, oct. 2003.

Ju Jing and Chunhua Wang, “A New current-mode differential Low Noise Amplifier,” ICSICT 2008, 9th International conference, pp. 1524-1527, oct. 2008.

Thomas H. Lee, “The Design of CMOS Radio-Frequency Integrated Circuit,” Cambridge University Press, 1998.

Shaikh K. Alam and Joanne DeGroat. “A 1.5-V 2.4 GHz Differential CMOS Low Noise Amplifier for Bluetooth and Wireless LAN Applications,” CircuitsAnd System, IEEE North-East Workshop on. P13-16 (2006)

Rogers, John, and Plett, Calvin, Radio Frequency Integrated Circuit Design,Norwood, MA: Artech House, 2003.

Walkey, David J., 97.398 Physical Electronics Course Notes, 2002.


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