UWB AMPLIFIER USING CMOS TECHNOLOGY FOR A 3.1-5-GHZ USING A CASCODE CURRENT REUSE STRUCTURE WITH INTER-STAGE INDUCTORS

KIRAN KUMARI, ABHISHEK TIWARI

Abstract


ABSTRACT:

 

An CMOS low noise amplifier (LNA) topology that combines a narrowband LNA with a Capacitor cross-coupled with inductively source degenerated differential LNA is proposed. The Capacitor cross-coupled with inductively source degenerated LNA provides wideband input matching with small noise figure (NF) degradation of the narrowband LNA input and flattens the gain. The proposed UWB amplifier is implemented in 0.18-/spl mu/m CMOS technology for a 3.1-5-GHz. Using a cascode current reuse structure with inter-stage inductors we achieved low power consumption and high power gain. This structure is based on two cascode configuration which provides a good output swing thus allowing the integration in low voltage technology. This configuration also permits good input impedance matching, low noise figure and high reverse isolation. Complete simulations of the circuit at 5.5-GHz center frequency.


Keywords


3.1-5-GHZ, CMOS TECHNOLOGY, CASCODE CURRENT, CAPACITOR.

Full Text:

PDF

References


REFERENCES

Suraj Sharma et.al. presented a paper on “Design of Low Noise Amplifier at 3-10GHz for Ultra Wideband Receiver” in September 2013 in IJIRCCE journal .

Mostafa yargholi et.al. presented a paper on “Resistive Feedback LNA With Dual Band Notch Filter for Suppressing WLAN Signals in UWB Receivers” in 2012 IEEE.

Rozi Rifin et.al presented a paper on “Design of an Inductor-Less LNA Using Resistive Feedback Topology for UWB Applications” in 2013 in RJASET Journal.

R.S.Sai Ram et.al. presented a paper on “ Analysis and Design of CMOS Cascode LNA for UWB Applications with Gain Enhancement and Out- Band Rejection Capability.” In July12 in IJERT.

Anuj Madan et.al presented a paper on “A 5 GHz 0.95 dB NF Highly Linear Cascode Floating-Body LNA in 180 nm SOI CMOS Technology” in IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 22, NO. 4, APRIL 2012

Ravinder Kumar et. Al. presented a paper on “DESIGN AND NOISE OPTIMIZATION OFRF LOW NOISE AMPLIFIER FOR IEEE STANDARD 802.11A WLAN” journal VLSICS Vol.3, No.2, April 2012.

Somit pandey presented a paper on “Analysis of Working of LNA in UWB Range” in AIJRFANS journal (13-212) in 2013.

Sohiful Anuar Zainol Murad et.al. presented a paper on “A Review of Low Noise Amplifiers' Topologies for Wireless Sensor Network” published in 2014 2nd International Conference on Electronic Design in journal Research Gate (375-379).

K. Yousef et.al. presented a paper on “A 2-16 GHz CMOS Current Reuse Cascaded Ultrawideband Low Noise Amplifier” year 2011 IEEE journal.

Xuan Chen, Quanyuan Feng and Shiyu Li, “Design of a 2.5GHz Differential CMOS LNA,” Progress In Electromagnetics Research Symposium, Cambridge, USA, pp. 203-206, Jul. 2008.

A. Nunez-Aldana, N. Dhanwada, A. Doboli, S. Ganesan, and R. Vemuri. “ A Methodology For Behavioral Synthesis Of Analog Systems ”. In Southwest Symposium on Mixed-Signal Design, pages162–167, 1999.

G. Van der Plas et.al. “AMGIE-A synthesis environment for CMOS analog integrated circuits”. InIEEE Transactions on Computer Aided Design of Integrated Circuits and

Systems, pages 1037–1058,2001.

R. A. Rutenbar and Georges G. E. Gielen and B. A. Antao. Computer-Aided Design of Analog Inte-grated Circuits and Systems. John Wiley & Sons, 2002.

Somesh kumar and Dr. Ravi Kumar, “A 1.8V and 2GHz Inductively Degenerated CMOS Low Noise Amplifier,” International Journal of Electronics Communication and Computer Engineering, Vol. 2, Issue 4, pp. 150-154, july 2012.

Reza Molavi, Shahriar Mirabbasi and Majid Hashemi, “ A Wideband CMOS LNA Design Approach,” IEEE International Symposium on Circuits and Systems, vol. 5, pp.

– 5110, May 2005.

Hong Qi and Zhang Jie, “A 1.5V Low Power CMOS LNA Design,” International

Symposium on Microwave, Antenna, Propagation and EMC Technologies for Wireless Communications, pp. 1379 - 1382 , Aug. 2007.

M. Muhamad and N.A Nordin, “An Area Efficient of 0.18µm LNA Using Power

Constraint Method,” IEEE Mathematical/Analytical Modeling and Computer

Simulation (AMS), PP. 606 – 609, May 2010.

Xiaohua Fan, Heng Zhang, and Edgar Sanchez-Sinencio, “A Noise Reduction and Linearity Improvement Technique for a Differential Cascode LNA”, IEEE J. Solid-State Circuits, vol.43, pp. 588-599, March 2008.


Refbacks

  • There are currently no refbacks.