IMPROVE EFFIECIECNY OF TRIPLE DES (TDES) ENCRYPTION ALGORITHM ON FPGA USING VHDL LANGUAGE

NANCY BADKUL, DILIP AHIRWAR, SUSHMITA BILANI JAIN

Abstract


Security issues are playing dominant role in today’s high speed communication systems.  Today’s connected society requires secure data encryption devices to preserve data privacy and authentication in critical applications. Of the several data encryption types, Data Encryption Standard (DES) and its variant Triple-DES (TDES) have emerged to be the most commonly used in varying applications. The Stratix-II devices with their extensive features and cost effectiveness compete effectively against ASICs and ASSPs. The design of the digital cryptographic circuit was implemented in a Stratix II series target device with the use of VHDL as the hardware description language. In order to confirm the expected behavior of these algorithms, the proposed design was extensively simulated, synthesized for different FPGA devices both in Spartan and Stratix II device families. The novelty and contribution of this work is in three folds:

                         i.Extensive simulation and synthesis of the proposed design targeted for various FPGA devices,

                       ii.Complete hardware implementation of encryption and decryption algorithms onto Stratix II series device based FPGA boards and,

                     iii.The experimental as well as implementation results compared to the implementations reported so far are quite encouraging.


Keywords


COMPONENT; FORMATTING; STYLE; STYLING; INSERT (KEY WORDS)

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References


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